EDN

Delivering advanced SystemVerilog verification capabilities to design teams

Some might say you need to be a full-fledged verification expert or specialist with experience using the latest object-oriented languages to tap into the productivity benefits of advanced verification ...
EDN

Using advanced logging techniques to debug & test SystemVerilog HDL code

SystemVerilog provides an advantage in addressing the verification complexity challenge—not simply as a new language for describing complex structures, but as a platform for driving a more efficient, ...
Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

Sutherland HDL, Inc. "Sutherland HDL, a leader in advanced SystemVerilog training, has been pleased to use Questa in our training workshops, and to be an evaluator of Questa 6.2 and AVM. Questa ...
Design-Reuse

TransEDA adds SystemVerilog support and Advanced Rule checking to its leading Verification Navigator tool suite

Eastleigh UK - Paris France, January 24, 2005 – TransEDA, the leader in coverage and ready-to-use verification solutions for electronic designs, today announces SystemVerilog support in new versions ...
Hackaday

What Is SystemVerilog, Really?

[Mark] starts a post from a bit ago with: “… maybe you have also heard that SystemVerilog is simply an extension of Verilog, focused on testing and verification.” This is both true and false, ...